Xiaomi AI Cube: Bandwidth Is Only Useful With Software Access
HARDWARE & DESIGN
Xiaomi AI Cube: Bandwidth Is Only Useful With Software Access
A prototype can run a large supplied model without exposing a general-purpose toolchain. That is the key question around Xiaomi's AI Cube. Its bandwidth and power claims deserve measurements, but a local-model buyer also needs to know which checkpoints and runtimes the user can actually choose.
In this article
For a buyer, the distinction is software access. A demonstration of a supplied model does not show whether users can load another checkpoint, choose a quantization or run an existing toolchain. That is the constraint to read alongside the bandwidth comparison.
Three custom chips in one box
The AI Cube isn't a Mac mini with a big NPU bolted in. Xiaomi wired three of its own chips together to make the point that it now controls the whole AI stack — the phone SoC, a high-bandwidth model accelerator, and an automotive chip all working on the same workload.
| Chip | Role | Specs that matter | Status |
|---|---|---|---|
| XRING O3 | General-purpose SoC | 10-core all-big-core CPU, 16-core G2-Ultra NX GPU, 200 TOPS NPU, first LPDDR6 support | Ships this fall in the 18 Fold |
| XRING O100 | High-bandwidth AI accelerator | 6nm 3D wafer-on-wafer stacking, 28,672 data lines, 1.22 TB/s near-memory bandwidth, ~330 tok/s with Xiaomi MiMo | Commercial 2027 |
| XRING D100 | Automotive AI chip | 3nm, 20-core CPU, 16-core NPU, up to 160 GB unified memory, 200B-parameter models | Commercial 2027 |
The three XRING chips inside the AI Cube, vendor-reported specs from Xiaomi's August 24 presentation.
The O100 is the interesting one. Xiaomi stacks three wafer layers — two high-speed AI DRAM wafers on top of a compute wafer — and bonds them vertically with 1.4µm hybrid bonding. The data paths go straight up instead of out to a memory channel, which is how it reaches 1.22 TB/s where a flagship phone's LPDDR5X manages maybe a sixteenth of that.
The prototype demonstration
It's a small tower in aerospace-grade aluminum, machined with 33,874 CNC-drilled holes because that case keeps 150 W of sustained work cool while it looks like a pebble-grey slab of Swiss cheese. Xiaomi frames it as a DGX Spark-shaped thing for the desk, but the box actually looks more like a compact NAS than a GPU workstation.
The AI Cube prototype. Aerospace-grade aluminum, 33,874 CNC precision holes, 150 W sustained (image: Xiaomi / Lei Jun).
The pitch, on one slide: O3 for phones, O100 for model inference, D100 for driving — all competing for the same package (image: Xiaomi, presentation slide).
The D100, Xiaomi's first 3nm in-house driving chip, shown as a render on stage (image: Xiaomi).
The bandwidth comparison and its limits
For a local LLM, the number that decides how fast text comes out isn't TOPS — it's memory bandwidth. Every token a model generates means re-reading the model weights from memory. A 120B model at 4-bit quantization is roughly 60 GB of weights, and the faster you can feed them to the compute, the faster tokens land. Xiaomi ate the cost of the pipeline at the physical layer instead of just clocking the NPU.
Memory bandwidth, the number that decides local-LLM speed. The AI Cube's figure is vendor-reported; DGX Spark and Mac Studio values are official (chart by the author).
The result is a local box Xiaomi says runs a 120B + 3B model pair, switching between them based on the task — the small model for millisecond everyday commands, the big one for deep reasoning. That dual-model fast/slow scheme is the same idea the big AI labs run in the datacenter, just on your desk at 150 W.
Software access and availability
Here's what the launch coverage glossed over. The number everyone quotes — 330 tokens per second — is a Xiaomi-lab number on Xiaomi's own optimized runtime running Xiaomi's MiMo models. That's a closed stack. The AI Cube has no CUDA, there's no XRING backend in llama.cpp, and the NPU's fast path is only reachable through Xiaomi's walled garden.
What does that mean in practice? If you want to load a random GGUF of the model you actually like, or run vLLM, or fine-tune, you're not going to get that 1.22 TB/s magic — you're offloading to whoever wrote a runtime for this chip, and right now that's Xiaomi. The hardware headline is real, but the software is the piece that makes or breaks a "local AI machine."
DGX Spark has a documented CUDA software path, which makes compatibility easier to investigate for an existing CUDA workload. The Cube demonstration does not establish an equivalent path. That difference concerns available software evidence, rather than a measured performance win for either machine.
The hardware claims justify further testing, especially the sustained bandwidth and power conditions. A purchase recommendation would also need a retail configuration, price and supported-model list. With the O100 and the other cited chip not scheduled for commercial availability until 2027 in this announcement, the Cube remains a prototype to follow rather than a priced alternative to buy from this article.
Related on this blog: Apple's M5 Ultra Mac Studio: A Real Local AI Machine, at Last · FreeToken Wants to Put Frontier MoE Models on Your Edge Machine
Sources: Xiaomi (Lei Jun, Aug 24 2026), VideoCardz, CnEVPost, IT之家, 36Kr/爱范儿. All performance figures are vendor-reported until independently verified. The memory-bandwidth chart draws on official figures for DGX Spark (273 GB/s, GB10) and Apple Mac Studio (M3 Ultra 819 GB/s, M4 Max 546 GB/s).
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